A New Approach for VDMOSFETs' Gate Oxide Degradation Based on Capacitance and Subthreshold Current Measurements Under Constant Electrical Stress
IEEE TRANSACTIONS ON ELECTRON DEVICES, cilt.65, sa.4, ss.1650-1652, 2018 (SCI-Expanded, Scopus)
- Yayın Türü: Makale / Tam Makale
- Cilt numarası: 65 Sayı: 4
- Basım Tarihi: 2018
- Doi Numarası: 10.1109/ted.2018.2808162
- Dergi Adı: IEEE TRANSACTIONS ON ELECTRON DEVICES
- Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus
- Sayfa Sayıları: ss.1650-1652
- İstanbul Üniversitesi-Cerrahpaşa Adresli: Evet
Özet
In this brief, we proposed a new gate oxide degradation model for vertical double diffused MOS devices under constant electrical stress. To form a complete model, we separated the changes associated with gate oxide and Si-SiO2 interface. We presented oxide trap-induced gate oxide and interface trap-induced Si-SiO2 interface degradation effects on the model, separately. We used capacitance measurements for gate oxide and subthreshold current measurements for Si-SiO2 interface degradation. We presented the survive of the stress-induced gate oxide and interface capacitances during stress time. We also expressed the mathematical expressions for parts of the proposed model.